The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices requires design features of 0.25 microns and under, such as 0.18 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor manufacturing technology.
The aggressive scaling of gate electrode dimensions into the deep submicron regime, such as less than about 0.25 microns, demands extremely shallow junctions to maintain good short channel characteristics and current drive. For example, semiconductor devices having design features of about 0.25 microns require a significantly reduced lightly doped drain (LDD) junction depth (X.sub.J) of less than about 800 .ANG.. Conventional methodology comprises ion implanting an N-type impurity having a low diffusion coefficient, typically arsenic (As). The formation of a sharp N-type impurity (N)-LDD junction requires the power supply voltage (V.sub.dd) to be reduced in order to maintain sufficient hot carrier reliability. While attractive from a power dissipation standpoint, a lower V.sub.dd compromises speed and current drive required for microprocessors, particularly for desktop applications. Thus, hot carrier injection (HCI) reliability has become the limiting factor for performance of N-channel MOSFETs, particularly as the design rules shrink. A reduction in the HCI lifetime is attributed to the sharp N-LDD junction which causes a high peak electric field in the channel region.
Adverting to FIG. 1, a conventional N-channel transistor comprises substrate 10 and gate electrode 11 formed thereon with gate oxide layer 12 therebetween. An N-LDD implant, for subsequently activated N-LDD region 13, is formed by ion implantation using the gate electrode as a mask, usually As because of its low diffusion coefficient, typically at an implantation dosage of about 1.times.10.sup.13 atoms/cm.sup.2 to about 1.times.10.sup.14 atoms/cm.sup.2 at an energy of about 10 KeV to about 30 KeV. Sidewall spacer 14 is then formed on the side surfaces of gate electrode 11 and ion implantation is conducted to form the source/drain region implant for the adjoining subsequently activated N-source/drain region 15 by ion implanting As at an implantation energy of about 1.times.10.sup.15 atoms/cm.sup.2 to about 1.times.10.sup.16 atoms/cm.sup.-2 at an energy of about 30 KeV to about 60 KeV. Activation annealing is then conducted at a temperature of about 1,000.degree. C. to about 1,100.degree. C. for about 10 seconds to about 60 seconds, to activate the N-LDD and source/drain regions. The HCI lifetime of such a conventional N-channel transistor is undesirably low due to a high peak electric field in the channel region caused by the sharp junction between N-LDD region 13 and P substrate 10.
D. Nayak et al., in "A Comprehensive Study of Performance and Reliability of P, As, and Hybrid As/P N-LDD Junctions for Deep-Submicron CMOS Logic Technology," IEEE Electron Device Letters, Vol. 18, No. 6, 1997, pp. 281-283, disclose a method of N-LDD junction grading to decrease the peak electric field in the channel, thereby improving the HCI lifetime. The disclosed technique comprises ion implanting As and P to form the N-LDD implant. While this technique was reported to improve the HCI lifetime in semiconductor devices of 0.35 micron technology, such a hybrid As/P-LDD technique cannot be directly applied to semiconductor devices having design features of about 0.25 microns and below, because the Off-current is increased to an unacceptably high level.
In copending application Ser. No. 08/924,644, filed Sep. 5, 1997, a method is disclosed comprising ion implanting a rapidly diffusing N-type impurity, such as P, into a doped (As) source/drain implant after sidewall spacer formation. Upon activation annealing, a graded N-type LDD junction is formed with an attendant significant increase in the HCI lifetime without an increase in the Off-current. In copending application Ser. No. 08/923,996, filed Sep. 5, 1997, a method is disclosed comprising forming a second sidewall spacer, after forming N-type impurity, e.g., As, moderately or heavily doped source/drain implants, and ion implanting a rapidly diffusing N-type impurity, such as P. Upon activation annealing, a P-containing region is formed having a graded junction extending below the source/drain region and sufficiently spaced apart from the channel region to reduce junction capacitance, thereby enabling higher circuit speeds.
As design rules decrease to 0.25 microns and under, the channel length of the channel region becomes smaller and smaller. Consequently, a higher electrical field is generated at the drain region causing hot carrier injection into the gate oxide, thereby degrading transistor performance. In the 0.25 micron regime and under, it is necessary to form the N-LDD implant, such as As, at an implantation dosage of about 10.sup.14 atoms cm.sup.-2 in order to maintain transistor performance. However, at such a dopant level in a 0.25 micron regime, the N-LDD region effectively shortens the channel length, thereby creating a high electrical field at the drain causing hot carrier injection into the gate dielectric with an attendant degradation in transistor performance.
There exists a need for semiconductor methodology and devices exhibiting an increased HCI lifetime without employing a high diffusivity dopant, thereby avoiding an increase in the X.sub.J, without adverse impact on the short channel effect, and without degrading transistor performance. There also exists a need for semiconductor methodology and devices having a design rule of about 0.5 microns and under with an increased HCI lifetime by simplified methodology.